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| G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) Features : 32K x 8-bit organization. Very high speed 12,15,20 ns. Low standby power. Fully static operation 5V10% power supply. TTL compatible I/O. Three state output. Chip enable for simple memory expansion. Available 300 mil SOJ, 28 pin TSOP and 330 mil SOP Packages. Industrial Grade Available (-40C ~ 85C). Description : GLT725608 is high performance 256K bit static random access memory organized as 32K by 8 bits and operate at a single 5 volt supply. Fabricated with G-Link Technology's very advanced CMOS submicron technology, GLT725608 offer a combination of features: very high speed and very low stand-by current. In addition, this device also supports easy memory expansion with an active LOW chip enable ( CE ) as well as an active LOW output enable ( OE ) and three state outputs. Pin Configurations : SOJ and SOP Function Block Diagram : G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -1- G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) Pin Descriptions: Name A0 - A14 CE OE WE Function Address Inputs Chip Enable Input Output Enable Input Write Enable Input Data Input and Data Output +5V Power Supply Ground I/O0 - I/O7 VCC GND Truth Table: Mode Not Selected (Power Down) Output Disabled Read Write Absolute Maximum Ratings: Ambient Temperature WE CE OE X H H L H L L L X H L X I/O Operation High Z High Z D OUT DIN VCC Current ICCSB , ICCSB1 ICC ICC ICC Operation Range : Range Commercial Temperature 0C to + 70C Vcc 5V 10% Under Bias...................................-10C to +80C Storage Temperature(plastic)....-55C to +125C Voltage Relative to GND.............-0.5V to + 7.0V Data Output Current..................................50mA Power Dissipation......................................1.0W 1.Stresses greater than those listed under ABSOLUTE MAXIMUM RATING may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Industrial -40C to 85C 5V 10% Capacitance (1)TA=25C,f=1.0MHZ : Sym. CIN CI/O Parameter Input Capacitance Input / output Capacitance conditions VIN = 0V VI/O = 0V Max. Unit 8 10 pF pF G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -2- G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) DC Characteristics Sym. VIL VIH ILI ILO VOL VOH ICC Parameter Test Conditions Min. Typ(1) -0.3 2.2 -5 -5 2.4 - Max. +0.8 VCC+0.3 5 5 0.4 -12 -15 -20 160 150 120 40 30 20 Unit V V A A V V mA mA mA Guaranteed Input Low Voltage (2) Guaranteed Input High Voltage (2) Input Leakage Current VCC= Max., VIN=0V to VCC Output Leakage Current V = Max., CE V CC IH Output Low Voltage VCC= Min., IOL =8mA Output High Voltage VCC= Min., IOH =-4mA Operating Power Supply V = Max., CE V , CC IL Current I =0mA., F= F (3) I/O max ICCSB Standby Power Supply Current ICCSB1 Power Down Power Supply Current VCC= Max., CE VIH, II/O=0mA., F= Fmax(3) VCC= Max., CE VCC.-0.2V, VINVCC. -0.2V or - 10 10 10 1. Typical characteristics are at VCC=5V, TA=25 2. These are absolute values with reject to device ground and all overshoots due to system or tester noise are included. 3. FMAX=1/tRC. Data Retention Sym. VDR Parameter VCC for Data retention Test Conditions VIN VCC -0.2V or VIN 0.2V VDR=2.0V VDR=3.0V CE VCC -0.2V, Min. 2.0 Typ(1) - Max. 5.5 30 50 - Unit V A A ns ns ICCDR(1) Data Retention Current tCDR tR Chip Deselect to Data Retention Time See Retention Waveform Operating Recovery Time 0 tRC(2) - 1. CE VDR -0.2V, VIN VDR -0.2V or VIN 0.2V. 2. tRC =Read Cycle Time. G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -3- G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) Low VCC Data Retention Waveform ( CE Controlled) AC Test Conditions Input Pulse Levels Input Rise and Fall Times Timing Reference Level 0V to 3.0V 3 ns 1.5V AC Test Loads and Waveforms AC Electrical Characteristics Read Cycle JEDEC Parameter Parameter Name Name tAVAX tRC Read Cycle Time tAVQV tE1LQV tGLQV tE1LQX tGLQX tE1HQZ tGHQZ tAXQX tAA tACS tOE tCLZ tOLZ tCHZ tOHZ tOH 725608-12 725608-15 725608-20 Parameter Min. Max. Min. Max. Min. Max. Unit Address Access Time Chip Select Access Time, CE Output Enable to Output Valid Chip Select to Output Low Z, CE Output Enable to Output in Low Z Chip Deselect to Output in High Z, CE Output Disable to Output in High Z Output Hold from Address Change 12 3 3 3 12 12 5 7 6 - 15 - 15 - 15 3 3 3 6 8 6 - 20 3 3 3 20 20 8 10 8 - ns ns ns ns ns ns ns ns ns G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -4- G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) Switching Waveform (Read Cycle) READ CYCLE 1 (1,2,4) READ CYCLE 2 (1,3,4) READ CYCLE 3 (1) Notes: 1. WE is High for READ Cycle. 2. Device is continuously selected CE VIL. 3. Address valid prior to or coincident with CE transition low and/or transition high. 4. OE VIL. 5. Transition is measured 200mV from steady state with CL=5pF. G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -5- G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) AC Electrical Characteristics Write Cycle JEDEC Parameter Parameter Name Name tAVAX tWC Write Cycle Time tE1LWH tAVWL tAVWH tWLWH tWHAX tE2LAX tWLQZ tDVWH tWHDX tWHQX tCW tAS tAW tWP tWR1 tWR2 tWHZ tDW tDH tOW 725608-12 Parameter Min. Max. 725608-15 Min. Max. 725608-20 Min. Max. Unit Chip Select to End of Write Address Set up Time Address Valid to End of Write Write Pulse Width Write Recovery Time, WE Write Recovery Time, CE Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time End of Write to Output Active 12 10 0 10 10 0 0 6 0 3 7 - 15 12 0 12 12 0 0 7 0 3 8 - 20 15 0 15 15 0 0 8 0 3 10 - ns ns ns ns ns ns ns ns ns ns ns Switching Waveforms(Write Cycle) WRITE CYCLE 1 (1) G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -6- G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) Switching Waveform (Write Cycle) WRITE CYCLE 2(1,6) Note: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap CE low and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, outputs remain in a high impedance state. 6. OE is continuously low ( OE =VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 200mV from steady state with CL=5pF. 11. tCW is measured from CE going low to the end of write. G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -7- G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) Ordering Information Part Number GLT725608-12J3 GLT725608-15J3 GLT725608-20J3 GLT725608-12TS GLT725608-15TS GLT725608-20TS GLT725608-12TC GLT725608-15TC GLT725608-20TC GLT725608-12FB GLT725608-15FB GLT725608-20FB SPEED 12ns 15ns 20ns 12ns 15ns 20ns 12ns 15ns 20ns 12ns 15ns 20ns POWER Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal Normal PACKAGE SOJ 300mil 28L SOJ 300mil 28L SOJ 300mil 28L TSOP 28L TSOPI 28L TSOPI 28L TSOPII 28L TSOPII 28L TSOPII 28L SOP 330mil 28L SOP 330mil 28L SOP 330mil 28L Parts Numbers (Top Mark) Definition : GLT 7 256 4 : DRAM 6 : Standard SRAM 7 : Cache SRAM 8 : Synchronous Burst SRAM -SRAM 064 : 8K 256 : 256K 512 : 512K 100 : 1M -DRAM 10 : 1M(C/EDO)* 11 : 1M(C/FPM)* 12 : 1M(H/EDO)* 13 : 1M(H/FPM)* 20 : 2M(EDO) 21 : 2M(FPM) 40 : 4M(EDO) 41 : 4M(FPM) 80 : 8M(EDO) 81 : 8M(FPM) 160 : 16M(EDO) 161 : 16M(FPM) 08 CONFIG. 04 : x04 08 : x08 16 : x16 32 : x32 I - 12 TC SPEED -SRAM 12 : 12ns 15 : 15ns 20 : 20ns 70 : 70ns -DRAM 35 : 35ns 40 : 40ns 45 : 45ns 50 : 50ns 60 : 60ns PACKAGE T : PDIP(300mil) TS : TSOP(Type I) TC : TSOP(Type ll) PL : PLCC FA : 300mil SOP FB : 330mil SOP FC : 445mil SOP J3 : 300mil SOJ J4 : 400mil SOJ P : PDIP(600mil) Q : PQFP TQ : TQFP VOLTAGE Blank : 5V L : 3.3V M : 2.5V N : 2.1V Temperature Range E : Extended Temperature I : Industrial Temperature Blank : Commercial Temperature G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -8- G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) Package Information 300mil 28 Lead Small Outline J-form Package (SOJ) G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. -9- G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) 28L (8x13.4 mm) Thin Small Outline Package (TSOP) Type I G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 10 - G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) 28L (8x20mm) Thin Small Outline Package (TSOP) Type I G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 11 - G -LINK GLT725608 Ultra High Performance 32K x 8 Bit CMOS STATIC RAM Feb, 2001(Rev.2.4) 330mil 28 Lead Thin Small Outline (Gull-Wing) Package (SOP) G-Link Technology 2701 Northwestern Parkway Santa Clara, CA 95051, U.S.A. G-Link Technology Corporation, Taiwan 6F, No. 24-2, Industry E, RD, IV, Science Based Industrial Park, Hsin Chu, Taiwan. - 12 - |
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